1. Field of the Invention
The present invention relates to multilayer capacitors, wiring boards, decoupling circuits, and high frequency circuits, which include the multilayer capacitors. More particularly, the present invention relates to multilayer capacitors that are very effective in high frequency circuits. In addition, the present invention relates to wiring boards, decoupling circuits, and high frequency circuits including the multilayer capacitors.
2. Description of the Related Art
Most conventional multilayer capacitors are formed of ceramic dielectric materials. In addition, each of these conventional multilayer capacitors has a main body including a plurality of laminated dielectric layers, and a plurality of pairs of first and second internal electrodes opposing each other via specified dielectric layers and alternately arranged in a direction in which the dielectric layers are laminated to form a plurality of capacitor units. First external terminal electrodes are located on the first end surface of the main body, and second external terminal electrodes are located on the second end surface thereof. The first internal electrodes are extended onto the first end surface of the main body to be electrically connected to the first external terminal electrodes. In addition, the second internal electrodes are extended onto the second end surface of the main body to be electrically connected to the second external terminal electrodes.
In the multilayer capacitor, for example, currents flow By from the second external terminal electrodes to the first external terminal electrodes. In this case, the currents flow from the second external terminal electrodes to the second internal electrodes and, then, flow from the second internal electrodes to the first internal electrodes passing through the dielectric layers. After this, the currents pass through the first internal electrodes to the first external terminal electrodes.
The equivalent circuit of a capacitor is shown as a circuit in which a capacitance (C), an equivalent series inductance (ESL), and the resistance (R) of an electrode are connected in series. In this case, R is referred to as an equivalent series resistance (ESR).
In the equivalent circuit, a resonant frequency f0 is determined by an equation f0=1/[2xcfx80xc3x97(Lxc3x97C)xc2xd]. The capacitor cannot function at a frequency higher than the resonant frequency. In other words, when the value of L, that is, the value of ESL is small, the resonant frequency f0 becomes high, so that the capacitor can be used at the higher frequency. It is considered that copper may be used as the material of internal electrodes to reduce the value of ESR. However, in order to use the capacitor in a microwave band, the capacitor must be capable of reducing ESL.
In addition, the reduction of ESL is required for a capacitor used as a decoupling capacitor connected to a power source circuit for supplying a power source to a MPU chip of a micro processing unit (MPU) of a workstation, a personal computer, or other suitable device.
Regarding this case, FIG. 16 is a block diagram illustrating an example of a connecting structure including a MPU 1 and a power source unit 2.
In FIG. 16, the MPU 1 has a MPU chip 3 and a memory 4. The power source unit 2 supplies a power source to the MPU chip 3. A decoupling capacitor 5 is connected to a power source circuit located between the power source unit 2 and the MPU chip 3. In addition, a signal circuit is located between the MPU chip 3 and the memory 4.
The decoupling capacitor 5 used in the MPU 1, like a typical type of decoupling capacitor, is used to smooth noise absorption and fluctuations in the power source. Moreover, recently, the operational frequency of the MPU chip 3 has been designed to be over 1 GHz. Thus, the MPU chip 3 needs to have high-speed performance. In order to satisfy this requirement, a quick power supply function is necessary. This is a function in which power is supplied in a few nanoseconds from the capacity of electricity charged in a capacitor, when power for starting-up is suddenly needed.
Thus, an inductance component provided in the decoupling capacitor 5 used in the MPU 1 is required to be as low as possible, for example, to be a few pH or lower. That is, a capacitor having lower inductance is desired.
More specifically, in the MPU chip 3, a DC current voltage of approximately 2.0V is applied, and a consumed power is approximately 24W. That is, a current of approximately 12A flows through the chip. In this case, there is provided an arrangement for reducing the consumption of power. When the MPU 1 is not operating, the MPU 1 is in a sleep mode, in which the amount of the consumed power is reduced to 1W or lower. When converted from the sleep mode to an active mode, it is necessary to supply power required for the active mode to the MPU chip 3 in a significantly short time, as shown below. At the operational frequency of 1 GHz, when converted from the sleep mode to the active mode, power needs to be supplied in 2 to 4 nanoseconds.
However, since the power source unit 2 cannot supply the power in such a short time, electrical charge accumulated in the decoupling capacitor 5 near the MPU chip 3 is released until the power source is supplied from the power source unit 2 to the MPU chip 3.
In the case of an MPU having an operational clock frequency exceeding 1 GHz, in order to perform the above function, the ESL of the decoupling capacitor 5 disposed near the MPU chip 3 needs to be a few pH or lower.
However, since the ESL of the above-mentioned conventional multilayer capacitor ranges from approximately 500 pH to 800 pH, this hardly satisfies the above necessary condition of being a few pH or lower. Regarding an inductance component occurring in the multilayer capacitor, magnetic flux, having a direction that is determined by the direction of a current flowing though the multilayer capacitor, is induced to produce a self-inductance component.
Under the aforementioned background, examples of the structures of multilayer capacitors capable of reducing .ESL are provided in Japanese Unexamined Patent Application Publication No. 2-256216, U.S. Pat. No. 5,880,925, Japanese Unexamined Patent Application Publication No. 2-159008, Japanese Unexamined Patent Application Publication No. 11-144996, and Japanese Unexamined Patent Application Publication No. 7-201651.
The ESL is reduced by cancellation of magnetic flux induced in the multilayer capacitor. For the cancellation of magnetic flux, the direction of a current flowing through the multilayer capacitor is diversified. In order to diversify the direction of the current, the number of terminal electrodes provided on the external surface of the main body of the capacitor is increased, thereby increasing the number of leading internal electrodes extended to be electrically connected to the terminal electrodes. Additionally, the leading internal electrodes are oriented in some directions.
For example, in each of Japanese Unexamined Patent Application Publication No. 2-256216, U.S. Pat. No. 5,880,925, and Japanese Unexamined Patent Application Publication No. 2-159008, there is provided a structure in which lead internal electrodes are extended onto two opposing side surfaces of the main body of a multilayer capacitor, which is a first conventional art.
In addition, Japanese Unexamined Patent Application Publication No. 11-144996 provides a structure in which leading internal electrodes are extended onto four side surfaces of the main body of a multilayer capacitor, which is a second conventional art.
Furthermore, Japanese Unexamined Patent Application Publication No. 7-201651 provides a structure in which leading internal electrodes are extended onto a main surface of the main body of a multilayer capacitor, which is a third conventional art.
When a focus is put on the reduction of ESL in the first to third conventional arts, in general, the second conventional art can achieve an ESL that is lower than the first conventional art. Moreover, the third conventional art can achieve an ESL that is lower than the second conventional art. In other words, in terms of the reduction of ESL, the third conventional art is the most effective.
However, the third conventional art has a problem in that it is difficult to obtain large capacitance when the ESL is reduced. This problem will be explained below.
In the multilayer capacitor of the third conventional art, conductive via-holes are formed in order to lead internal electrodes onto the main surface of the main body of the multilayer capacitor. First and second internal electrodes opposing each other via dielectric layers are both led out onto one of the main surfaces of the capacitor unit so that capacitor units are produced. In this situation, even though only one pair of first and second internal electrodes is provided, a conductive via-hole connected to one of the first and second internal electrodes needs to be extended in such a manner that the conductive via-hole passes through the other internal electrode. Thus, since the other internal electrode needs to be insulated from the conductive via-hole, a gap must be formed around the part of the other internal electrode, through which the conductive via-hole passes.
Furthermore, in order to obtain larger capacitance in the multilayer capacitor, a plurality of first and second internal electrodes are alternately arranged in a direction in which dielectric layers are laminated to define a plurality of capacitor units, which are connected in parallel via conductive via-holes.
Thus, a first conductive via-hole connected to the first internal electrodes is extended in a manner that the first conductive via-hole electrically connects the plurality of first internal electrodes to each other while passing through the second internal electrodes. In addition, a second conductive via-hole connected to the second internal electrodes is extended in a manner that the second conductive via-hole electrically connects the plurality of second internal electrodes to each other while passing through the first internal electrodes.
Thus, in each of the second internal electrodes, it is necessary to form a gap around a part where the first conductive via-hole passes through, by which the first conductive via-hole and the second internal electrodes need to be insulated from each other. Similarly, in each of the first internal electrodes, it is necessary to form a gap around a part where the second conductive via-hole passes through, by which the second conductive via-hole and the first internal electrodes need to be insulated from each other.
However, since the above gap formation leads to reduction of the areas of the internal electrodes, large capacitance cannot be obtained. In addition, in the multilayer capacitor according to the third conventional art, in order to reduce the ESL even more, it is necessary to narrow the gaps between the plurality of conductive via-holes while increasing the number of the conductive via-holes. As a result, this arrangement causes a serious problem in that the areas of the internal electrodes are reduced due to the further reduction of ESL, and large capacitance cannot thereby be obtained due to the reduction of the areas of the internal electrodes.
As described above, in the third conventional art, it is difficult to satisfy both demands of reducing the ESL and obtaining large capacitance. That is, the third conventional art cannot satisfactorily meet the demand for capacitance that is large enough to provide a large amount of power required by the high-speed operation of the MPU.
Examples of the structures of multilayer capacitors capable of increasing capacitance are provided in U.S. patent application Ser. No. 09/751,612, filed on Dec. 29, 2000, entitled xe2x80x9cMultiple Tier Array Capacitor and Methods of Fabrication Therefor,xe2x80x9d which is incorporated herein by reference.
The multilayer capacitor embodiments described in that application include multiple xe2x80x9ctiersxe2x80x9d of capacitance. Similar to the third conventional art described above, via-holes are formed in order to lead internal electrodes onto the top and/or bottom main surfaces of the capacitor. However, each xe2x80x9ctierxe2x80x9d includes a different number of via holes that lead the tiers"" layers to the surfaces. For example, one tier has a relatively large number of via holes, resulting in a relatively low ESL. However, the many gaps in the conductive layers also result in a relatively low capacitance. Other tiers, have smaller numbers of via holes, resulting in fewer gaps and relatively larger capacitance. However, the fewer via holes also result in a relatively higher ESL than the first tier. Accordingly, the ESL and capacitance of each tier varies. Although this solution satisfies both demands of reducing the ESL and obtaining large capacitance, further reductions in ESL are desirable as the power required by the high-speed operation of the MPU continues to increase.
In order to overcome the problems described above, preferred embodiments of the present invention provide a multilayer capacitor that minimizes ESL and achieves a very large capacitance.
In addition, preferred embodiments of the present invention overcome the problems described above by providing a multilayer capacitor that greatly increases capacitance, minimizes inductance, while reducing the cost and difficulty of manufacturing such a novel multilayer capacitor.
In addition, in order to overcome the problems described above, preferred embodiments of the present invention provide a method of fabricating a capacitor, a wiring board, a decoupling circuit, and a high frequency circuit incorporating the unique multilayer capacitor described in the preceding paragraph.
According to a first preferred embodiment of the present invention, a multilayer capacitor includes a main body having a first main surface and a second main surface opposing each other, at least one side surface connecting the first and second main surfaces, and a plurality of laminated dielectric layers. A first main surface terminal electrode and a second main surface terminal electrode are provided on the first main surface of the main body. A first side surface terminal electrode and a second side surface terminal electrode are disposed on at least the side surface of the main body. The main body is divided into a low ESL section on the first main-surface side and a high capacitance section on the second main-surface side.
The low ESL section includes a first low ESL internal electrode and a second low ESL internal electrode opposing each other via a specified dielectric layer, a first conductive via-hole electrically connecting the first low ESL internal electrode to the first main surface terminal electrode and a second conductive via-hole electrically connecting the second low ESL internal electrode to the second main surface terminal electrode.
The high capacitance section includes a first high capacitance internal electrode and a second high capacitance internal electrode opposing each other via a specified dielectric layer, and a first leading electrode electrically connecting the first high capacitance internal electrode to the first side surface terminal electrode and a second leading electrode electrically connecting the second high capacitance internal electrode to the second side surface terminal electrode.
Preferably, in the multilayer capacitor according to various preferred embodiments of the present invention, a plurality of pairs of the first and second main surface terminal electrodes, and the first main surface terminal electrodes and the second main surface terminal electrodes are adjacent to each other.
In addition, preferably, when a plurality of pairs of the first and second side surface terminal electrodes is provided, the first side surface terminal electrodes and the second side surface terminal electrodes are adjacent to each other.
Furthermore, preferably, the main body of the multilayer capacitor has four side surfaces, on each of which the first and second side surface terminal electrodes are disposed. In this case, preferably, the first and second side surface terminal electrodes are adjacent to each other via the four side surfaces of the main body.
In the multilayer capacitor according to various preferred embodiments of the present invention, preferably, the first and second side surface terminal electrodes are arranged in a direction in which the first and second main surface terminal electrodes are arranged, the second side surface terminal electrodes are adjacent to the first main surface terminal electrodes, and the first side surface terminal electrodes are adjacent to the second main surface terminal electrodes.
In addition, the length of the first conductive via-hole may differ from the length of the second conductive via-hole.
In addition, the first conductive via-hole may be formed in the periphery of the first low ESL internal electrode and the second conductive via-hole may be formed in the periphery of the second low ESL internal electrode.
In addition, the multilayer capacitor of various preferred embodiments of the present invention may further include a third leading electrode electrically connecting the first low ESL internal electrode to the first side surface terminal electrode and a fourth leading electrode electrically connecting the second low ESL internal electrode to the second side surface terminal electrode.
Preferably, in this case, the first low ESL internal electrode and the first high capacitance internal electrode are electrically connected to the same first side surface terminal electrode, and the second low ESL internal electrode and the second high capacitance internal electrode are electrically connected to the same second side surface terminal electrode.
In the above-described multilayer capacitor, a current capacitance that the multilayer capacitor can provide is determined by the cross-sectional areas of the side surface terminal electrodes. Therefore, preferably, the total cross-sectional area of the first and second side surface terminal electrodes is larger than the total cross-sectional area of the first and second conductive via-holes. More specifically, it is preferable that the total cross-sectional area of the first and second side surface terminal electrodes is substantially equal to or more than approximately 5.0xc3x9710xe2x88x924 mm2, and more preferably, it is substantially equal to or more than approximately 1.0xc3x9710xe2x88x922 mm2.
In addition, the multilayer capacitor of various preferred embodiments of the present invention may further include a third conductive via-hole electrically connecting at least one of the first low ESL internal electrode and the second low ESL internal electrode to at least one of the first high capacitance internal electrode and the second high capacitance internal electrode.
Furthermore, the multilayer capacitor of various preferred embodiments of the present invention may further include a third leading electrode electrically connecting the first low ESL internal electrode to the first side surface terminal electrode, a fourth leading electrode electrically connecting the second low ESL internal electrode to the second side surface terminal electrode, and a third conductive via-hole electrically connecting at least one of the first low ESL internal electrode and the second low ESL internal electrode to at least one of the first high capacitance internal electrode and the second high capacitance internal electrode. In this multilayer capacitor, the first low ESL internal electrode and the first high capacitance internal electrode are electrically connected to the same first side surface terminal electrode, and the second low ESL internal electrode and the second high capacitance internal electrode are electrically connected to the same second side surface terminal electrode.
In this case, a current capacitance that the multilayer capacitor can provide is determined by the total cross-sectional area of the first and second side surface terminal electrodes and the third conductive via-hole. Thus, preferably, the total cross-sectional area of the first and second side surface terminal electrodes and the third conductive via-hole is substantially equal to or more than approximately 5.0xc3x9710xe2x88x924 mm2, and more preferably, it is substantially equal to or more than approximately 1.0xc3x9710xe2x88x922 mm2.
In addition, preferably, the first and second side surface terminal electrodes have portions that extend to at least one of the first and second main surfaces of the main body.
When the first and second side surface terminal electrodes have portions extending to the first main surface of the main body, preferably, the first and second main surface terminal electrodes and the first and second side surface terminal electrodes have lengths that are substantially equal to or more than 1.0xc3x9710xe2x88x922 mm on the first main surface of the main body.
When the first and second side surface terminal electrodes having portions extending to both the first and second main surfaces of the main body, preferably, the first and second main surface terminal electrodes have lengths that are substantially equal to or more than approximately 1.0xc3x9710xe2x88x922 mm on the first main surface of the main body, and the first and second side surface terminal electrodes have lengths that are substantially equal to or more than approximately 1.0xc3x9710xe2x88x922 mm on the first and second main surfaces of the main body.
Furthermore, preferably, the first low ESL internal electrode and the first high capacitance internal electrode have substantially the same outer configuration, and the second low ESL internal electrode and the second high capacitance internal electrode have substantially the same outer configuration.
Furthermore, the multilayer capacitor of various preferred embodiments of the present invention may be used as a decoupling capacitor connected to a power source circuit used for a MPU chip incorporated in a micro-processing unit.
According to yet another preferred embodiment of the present invention, there is provided a wiring board incorporating the multilayer capacitor described above or containing the same therein.
The wiring board of other preferred embodiments of the present invention includes a MPU chip disposed in a micro-processing unit, a power source conductive wire for supplying a power source used for the MPU chip, and a ground-side conductive wire. In this wiring board, one of the first main surface terminal electrode and the second main surface terminal electrode of the multilayer capacitor, and one of the first side surface terminal electrode and the second side surface terminal electrode thereof are electrically connected to the power source conductive wire, and the remaining main surface terminal electrode and the remaining side surface terminal electrode are electrically connected to the ground-side conductive wire.
Preferably, the multilayer capacitor incorporating the above-described wiring board is arranged in such a manner that the first main surface of the main body thereof faces toward the MPU chip.
According to another preferred embodiment of the present invention, a decoupling circuit includes the multilayer capacitor according to the other preferred embodiments of the present invention.
Furthermore, according to yet another preferred embodiment of the present invention, a high frequency circuit includes the multilayer capacitor according to the other preferred embodiments of the present invention.
According to another preferred embodiment of the present invention, a capacitor includes a first tier of capacitance, which includes multiple first layers of patterned conductive material separated by layers of dielectric material. A first number of first capacitor vias extend from a top surface of the capacitor through the multiple first layers, where some of the first capacitor vias make electrical contact with every other one of the multiple first layers, and others of the first capacitor vias make electrical contact with a remainder of the multiple first layers. The capacitor also includes a second tier of capacitance, electrically connected to the first tier of capacitance, which includes multiple second layers of patterned conductive material. A second number of second capacitor vias extend through the multiple second layers, where some of the second capacitor vias make electrical contact with every other one of the multiple second layers, and others of the second capacitor vias make electrical contact with a remainder of the multiple second layers. The capacitor also includes a first side surface terminal electrode and a second side surface terminal electrode disposed on at least one side surface of the capacitor, where the first side surface terminal electrode makes electrical contact with some of the multiple first layers and multiple second layers, and the second side surface terminal electrode makes electrical contact with others of the multiple first layers and multiple second layers.
According to another preferred embodiment of the present invention, a method for fabricating a capacitor includes fabricating a multi-layer structure, which includes a first tier of capacitance and a second tier of capacitance electrically connected to the first tier of capacitance. The first tier has multiple first layers of patterned conductive material separated by layers of dielectric material, and the second tier has multiple second layers of patterned conductive material. The method also includes forming a first number of first capacitor vias, which extend from a top surface of the capacitor through the multiple first layers, where some of the first capacitor vias make electrical contact with every other one of the multiple first layers, and others of the first capacitor vias make electrical contact with a remainder of the multiple first layers. The method also includes forming a first side surface terminal electrode and a second side surface terminal electrode disposed on at least one side surface of the capacitor, where the first side surface terminal electrode makes electrical contact with some of the multiple first layers and multiple second layers, and the second side surface terminal electrode makes electrical contact with others of the multiple first layers and multiple second layers.